1. Field of the Invention
The invention generally relates to multi-frequency clocks. In particular, the invention is related to a clock switch in an integrated circuit chip that multiplexes asynchronous clock signals to generate a multi-frequency clock signal.
2. Background
Multi-frequency clocks are increasingly being used in integrated circuit chips to support a wide variety of applications. For example, a multi-frequency clock may be used to generate signals for varying the amount of vibration generated by a motor in a hand-held game controller or the intensity of an LED in an LED-based display. These clocks can also be used to conserve power in battery-operated devices such as cellular telephones, game controllers, Bluetooth® devices, or the like. In these devices, a multi-frequency clock can be used to provide an accurate high-speed clock during normal operation and to provide a less accurate low-speed clock for keeping system functions alive while operating in a power-saving mode. The low-speed clock consumes less power than the high-speed clock.
To generate a multi-frequency clock, it is often necessary to switch the source of a clock line while the chip is running. This is typically achieved by multiplexing two different frequency clock sources in hardware and controlling the multiplexer select line using internal logic.
In a clock switch that multiplexes two different frequency clock sources as described above, there is a risk of generating a “glitch” on the clock output line when switching from one clock source to the other. As used herein, the term “glitch” refers to irregular pulses generated on the clock output line of a clock switch that may or may not be interpreted as logic changes by other components internal or external to the chip. Such glitches are undesirable because they can cause functional errors to occur in sequential logic downstream of the clock switch.
FIG. 1 illustrates one conventional design for a clock switch that is designed to avoid glitches on the clock output line. In particular, FIG. 1 depicts a clock switch 100 that multiplexes two asynchronous clock sources (“CLK1” and “CLK2”) to generate a multi-frequency clock output signal (“CLOCK_OUT”) under the control of a clock selection signal (“SELECT”).
Clock switch 100 avoids glitches in part through the inclusion of a cross-coupled feedback loop that ensures that the selection of either of the two clock sources can only occur after the other clock source has been de-selected. Because the cross-coupled feedback loop operates to combine signals from different clock domains, D flip-flops 102 and 106 are included along each clock selection path to perform a synchronization function. In particular, by respectively latching received data at the rising edge of CLK1 or CLK2, D flip-flops 102 and 106 operate to minimize potential meta-stability caused by the asynchronous nature of the SELECT signal, the feedback signals and the clock source signals.
Clock glitches are further avoided by clock switch 100 through the use of D flip-flops 104 and 108, which respectively operate to register the clock select signal at the negative edge of CLK1 or CLK2. This prevents changes from occurring at the output of the clock switch while either clock sources is at a high level, thereby avoiding chopping of the output clock.
FIG. 2 is a timing diagram 200 that shows the states of signals CLK1, CLK2, SELECT and CLOCK_OUT before, during, and after a change-over from clock source CLK1 to CLK2. As shown in FIG. 2, before a point in time indicated by dashed line 202 (“time 202”), SELECT is in a logic low state and CLOCK_OUT reflects the state of CLK1. At time 202, SELECT transitions to a logic high state. However, the propagation of CLK1 continues until a subsequent time 204 after a rising and falling edge of CLK1 due to the operation of D flip-flops 102 and 104. Then, propagation of CLK2 is started at a further subsequent time 206 after a rising and falling edge of CLK2 due to the further operation of D flip-flops 106 and 108.
Although conventional clock switch 100 avoids generating glitches on the clock output line, the design used by clock switch 100 presents certain disadvantages. For example, because clock switch 100 employs a cross-coupled feedback loop that interconnects each clock selection path, it is not test-friendly. Furthermore, the cross-coupled feedback loop may cause potential race conditions in the circuit. Additionally, conventional clock switch 100 requires reset pins on the D flip-flops in order to place the circuit into a known state.
What is needed, then, is an improved clock switch that avoids the foregoing disadvantages of conventional solutions. In particular, what is needed is a clock switch that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The desired clock switch should not include a cross-coupled feedback loop, thus rendering the clock switch more test-friendly and avoiding potential race conditions in the switch. The desired clock switch should further be useable with asynchronous clock sources having a variety of different clock frequencies and phases.